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freescale semiconductor data sheet: technical data document number: MC9S08JS16 rev. 4, 4/2009 ? freescale semiconductor, inc., 2008-2009. all rights reserved. this document contains information on a prod uct under development. freescale reserves the right to change or discontinue this product without notice. MC9S08JS16 features: ? 8-bit hcs08 central processor unit (cpu) ? 48 mhz hcs08 cpu (central processor unit) ? 24 mhz internal bus frequency ? support for up to 32 interrupt/reset sources ? memory options ? up to 16 kb of on-chip in-circuit programmable flash memory with block protection and security options ? up to 512 bytes of on-chip ram ? 256 bytes of usb ram ? clock source options ? clock source options include cr ystal, resonator, external clock ? mcg (multi-purpose clock generator) ? pll and fll; internal reference clock with trim adjustment ? system protection ? optional computer operating properly (cop) reset with option to run from independent 1 khz internal clock source or the bus clock ? low-voltage detection ? illegal opcode detection with reset ? illegal address detection with reset ? power-saving modes ? wait plus two stops ? usb bootload ? mass erase entire flash array ? partial erase flash array ? erase all flash blocks except for the first 1 kb of flash ? program flash ? peripherals ? usb ? usb 2.0 full-speed (12 mbps) with dedicated on-chip 3.3 v regulator and transceiver; supports endpoint 0 and up to 6 additional endpoints ? spi ? one 8- or 16-bit selectable serial peripheral interface module with a receive data buffer hardware match function ? sci ? one serial communicat ions interface module with optional 13 bit break. full duplex non-return to zero (nrz); lin master extend ed break generation; lin slave extended break detec tion; wakeup on active edge ? mtim ? one 8-bit modulo counter with 8-bit prescaler and overflow interrupt ? tpm ? one 2-channel 16-bit timer/pulse-width modulator (tpm) module; selectable input capture, output compare, and edge-aligned pwm capability on each channel; timer module may be configured for buffered, centered pwm (cpwm) on all channels ? kbi ? 8-pin keyboard interrupt module ? rtc ? real-time counter with binary- or decimal-based prescaler ? crc ? hardware crc generator circuit using 16-bit shift register; crc16-cc itt compliancy with x 16 +x 12 +x 5 +1 polynomial ? input/output ? software selectable pullups on ports when used as inputs ? software selectable slew rate control on ports when used as outputs ? software selectable drive stre ngth on ports when used as outputs ? master reset pin and power-on reset (por) ? internal pullup on reset , irq, and bkgd/ms pins to reduce customer system cost ? package options ? 24-pin quad flat no-lead (qfn) ? 20-pin small outline ic package (soic) MC9S08JS16 series covers: MC9S08JS16 mc9s08js8 MC9S08JS16l mc9s08js8l 20 w-soic case 751d 24 qfn case 1982-01 tbd
MC9S08JS16 series mcu data sheet, rev. 4 freescale semiconductor 2 table of contents 1 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3.1 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . .6 3.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .6 3.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . .7 3.4 electrostatic discharge (esd ) protection characteristics8 3.5 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.6 supply current characteristics . . . . . . . . . . . . . . . . . . .15 3.7 external oscillator (xosc) characteristics . . . . . . . . .17 3.8 mcg specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.9 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.9.1 control timing . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.9.2 timer/pwm (tpm) module timing. . . . . . . . . . 20 3.10 spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.11 flash specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.12 usb electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1 package information . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2 mechanical drawings. . . . . . . . . . . . . . . . . . . . . . . . . . 26 revision history to provide the most up-to-date information, the re vision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to ve rify you have the latest information available, refer to: http://freescale.com/ the following revision history table summariz es changes contained in this document. revision date description of changes 1 9/1/2008 initial public released 2 1/8/2009 in ta bl e 7 , changed the parameter description of ri dd and s3i dd, the typicals of ri dd were changed as well. 3 3/9/2009 corrected the 24-pin qfn case number and doc. number information. 4 4/24/2009 added new parts information about MC9S08JS16l and mc9s08js8l. related documentation find the most current versions of all documents at: http://www.freescale.com reference manual (MC9S08JS16rm) contains extensive product informati on including modes of operation, memory, resets and interrupts, register defin ition, port pins, cpu, and all module information.
mcu block diagram MC9S08JS16 series mcu data sheet, rev. 4 freescale semiconductor 3 1 mcu block diagram the block diagram, figure 1 , shows the structure of the MC9S08JS16 series mcu. figure 1. MC9S08JS16 series block diagram v ss v dd port b 8-bit keyboard interrupt module (kbi) user flash (in bytes) user ram (in bytes) on-chip ice and debug module (dbg) hcs08 core cpu notes: 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pu llup/pulldown device if irq is enabled (irqpe = 1). pulldown is enabled if rising edge detect is selected (irqedg = 1). 3. irq does not have a clamp diode to v dd . irq must not be driven above v dd . 4. reset contains integrated pullup device if ptb1 enabled as reset pin function (rstpe = 1). 5. pin contains integrated pullup device. 6. when pin functions as kbi (kbipen = 1) and associated pin is configured to enable the pullup device, kbedgn can be used to reconfigure the pullup as a pulldown device. pta2/kbip2/mosi port a hcs08 system control resets and interrupts modes of operation power management voltage regulator cop irq lvd low-power oscillator multi-purpose clock generator (mcg) reset 2-channel timer/pwm module (tpm) pta3/kbip3/spsck bkgd/ms irq kbipx tclk tpmch0 tpmch1 extal xtal usb usb endpoint module ram full speed usb transceiver usbdp usbdn pta6/kbip6/rxd pta7/kbip7/txd real-time counter (rtc) pta4/kbip4/ss pta5/kbip5/tpmch1 8 system usb 3.3 v voltage regulator v usb33 512 MC9S08JS16 = 16,384 v ssosc pta0/kbip0/tpmch0 pta1/kbip1/miso ptb3/blms ptb2/bkgd/ms ptb0/irq/tclk ptb1/reset ptb5/extal ptb4/xtal serial peripheral interface module (spi) spsck ss miso mosi 8-/16-bit 8-bit modulo timer module (mtim) interface module (sci) serial communications rxd txd bdc bootloader rom (in bytes) 4096 16-bit cyclic redundancy module (crc) check generator mc9s08js8 = 8,192 MC9S08JS16l = 16,384 mc9s08js8l = 8,192
MC9S08JS16 series mcu data sheet, rev. 4 pin assignments freescale semiconductor 4 2 pin assignments this section shows the pin assignments in the packages available for the MC9S08JS16 series. table 1. pin availability by package pin-count pin number (package) <-- lowest priority --> highest 24 (qfn) 20 (soic) port pin alt 1 alt 2 1 4 ptb0 irq tclk 2 5 ptb1 reset 3 6 ptb2 bkgd ms 4 7 ptb3 blms 5 8 pta0 kbip0 tpmch0 6?nc 7 9 pta1 kbip1 miso 8 10 pta2 kbip2 mosi 9 11 pta3 kbip3 spsck 10 12 pta4 kbip4 ss 11 13 v dd 12 ? nc 13 14 v ss 14 15 usbdn 15 16 usbdp 16 17 v usb33 17 18 pta5 kbip5 tpmch1 18 ? nc 19 19 pta6 kbip6 rxd 20 20 pta7 kbip7 txd 21 1 ptb4 xtal 22 2 ptb5 extal 23 3 v ssosc 24 ? nc
pin assignments MC9S08JS16 series mcu data sheet, rev. 4 freescale semiconductor 5 figure 2. MC9S08JS16 series in 24-qfn package figure 3. MC9S08JS16 series in 20-pin soic package usbdn ptb3/blms 1 2 3 4 5 pta0/kbip0/tpmch0 81011 7 17 23 ptb2/bkgd/ms 13 14 15 16 22 21 20 19 ptb5/extal v ssosc pta5/kbip5/tpmch1 v usb33 v dd pta4/kbip4/ss pta2/kbip2/mosi pta1/kbip1/miso pta7/kbip7/txd ptb4/xtal pta3/kbip3/spsck ptb1/reset ptb0/irq/tclk usbdp v ss pta6/kbip6/rxd 24-pin qfn 12 nc 6 nc v ss nc 18 24 nc 9 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 pta3/kbip3/spsck pta4/kbip4/ss usbdp usbdn v usb33 pta5/kbip5/tpmch1 v dd v ss v ssosc ptb0/irq/tclk ptb1/reset pta0/kbip0/tpmch0 pta1/kbip1/miso pta2/kbip2/mosi pta7/kbip7/txd pta6/kbip6/rxd ptb5/extal ptb4/xtal ptb2/bkgd/ms ptb3/blms
MC9S08JS16 series mcu data sheet, rev. 4 electrical characteristics freescale semiconductor 6 3 electrical characteristics this chapter contains electri cal and timing specifications. 3.1 parameter classification the electrical parameters shown in this supplem ent are guaranteed by various methods. to give the customer a better understanding, the following classi fication is used and the parameters are tagged accordingly in the tabl es where appropriate: note the above classifications are used in the column labeled ?c? in applicable tables of this data sheet. 3.2 absolute maximum ratings absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond th e limits specified in table 3 may affect device reliability or cause permanent damage to the device. for functiona l operating conditions, refer to the re maining tables in this section. this device contains circuitry protect ing against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be ta ken to avoid application of any voltages higher than maximum-rated voltages to this high- impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either v ss or v dd ). table 2. parameter classifications p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characterization by measuring a statistically relevant sample si ze across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unle ss otherwise noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations. table 3. absolute maximum ratings rating symbol value unit supply voltage v dd 2.7 to 5.5 v input voltage v in ?0.3 to v dd + 0.3 v instantaneous maximum current single pin limit (applies to all port pins) 1, 2, 3 i d 25 ma maximum current into v dd i dd 120 ma storage temperature t stg ?55 to 150 c maximum junction temperature t j 150 c
electrical characteristics MC9S08JS16 series mcu data sheet, rev. 4 freescale semiconductor 7 3.3 thermal characteristics this section provides information about operating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and it is user-deter mined rather than being controlled by the mcu design. in order to take p i/o into account in power calculations, determine the difference between actual pin voltage and v ss or v dd and multiply by the pin current for each i/o pin. ex cept in cases of unusuall y high pin current (heavy loads), the difference between pin voltage and v ss or v dd will be very small. the average chip-junction temperature (t j ) in c can be obtained from: t j = t a + (p d ja ) eqn. 1 where: t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w 1 input must be current limited to the value spec ified. to determine the value of the required current-limiting resistor, calculate resistance values for positive (v dd ) and negative (v ss ) clamp voltages, then use the larger of the two resistance values. 2 all functional non-supply pins are internally clamped to v ss and v dd . 3 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the m cu is not consuming power. examples are: if no system clock is present, or if the clock rate is very low which would reduce overall power consumption. table 4. thermal characteristics rating symbol value unit operating temperature range (packaged) t a t l to t h -40 to 85 c thermal resistance 1,2,3,4 24-pin qfn 1s 2s2p 20-pin soic 1s 2s2p 1 junction temperature is a function of die si ze, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, am bient temperature, air flow, power dissipation of other components on the board, and board thermal resistance 2 junction to ambient natural convection 3 1s ? single layer board, one signal layer 4 2s2p ? four layer board, 2 signal and 2 power layers ja 92 33 86 58 c/w
MC9S08JS16 series mcu data sheet, rev. 4 electrical characteristics freescale semiconductor 8 p d = p int + p i/o p int = i dd v dd , watts ? chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications, p i/o << p int and can be neglecte d. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k (t j + 273 c) eqn. 2 solving equation 1 and equation 2 for k gives: k = p d (t a + 273 c) + ja (p d ) 2 eqn. 3 where k is a constant pertaining to the pa rticular part. k can be determined from equation 3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equation 1 and equation 2 iteratively for any value of t a . 3.4 electrostatic discharge (e sd) protection characteristics although damage from static disc harge is much less common on th ese devices than on early cmos circuits, normal handling precautions must be used to avoid exposure to static discharge. qualification tests are performed to ensure that these devices can withstand exposure to reas onable levels of static without suffering any permanent damage. this devi ce was qualified to aec-q 100 rev e. a device is considered to have failed if, after exposure to esd pulses, the device no longer meets the device specification requirements. complete dc parametric and functional testi ng is performed per the applicable device specification at room temperature followed by hot temperatur e, unless specified otherwise in the device specification. 3.5 dc characteristics this section includes information about power supply requirements, i/o pin char acteristics, and power supply current in various operating modes. table 5. esd protection characteristics parameter symbol value unit esd target for machine model (mm) ? mm circuit description v thmm 200 v esd target for human body model (hbm) ? hbm circuit description v thhbm 2000 v table 6. dc characteristics num c parameter symbol min typical 1 max unit 1 operating voltage 2 ? 2.7 ? 5.5 v
electrical characteristics MC9S08JS16 series mcu data sheet, rev. 4 freescale semiconductor 9 2p output high voltage ? low drive (ptxdsn = 0) 5 v, i load = ?2 ma 3 v, i load = ?0.6 ma 5 v, i load = ?0.4 ma 3 v, i load = ?0.24 ma v oh v dd ? 1.5 v dd ? 1.5 v dd ? 0.8 v dd ? 0.8 ? ? ? ? ? ? ? ? v output high voltage ? high drive (ptxdsn = 1) 5 v, i load = ?10 ma 3 v, i load = ?3 ma 5 v, i load = ?2 ma 3 v, i load = ?0.4 ma v dd ? 1.5 v dd ? 1.5 v dd ? 0.8 v dd ? 0.8 ? ? ? ? ? ? ? ? 3p output low voltage ? low drive (ptxdsn = 0) 5 v, i load = 2 ma 3 v, i load = 0.6 ma 5 v, i load = 0.4 ma 3 v, i load = 0.24 ma v ol 1.5 1.5 0.8 0.8 ? ? ? ? ? ? ? ? v output low voltage ? high drive (ptxdsn = 1) 5 v, i load = 10 ma 3 v, i load = 3 ma 5 v, i load = 2 ma 3 v, i load = 0.4 ma 1.5 1.5 0.8 0.8 ? ? ? ? ? ? ? ? 4p output high curr ent ? max total i oh for all ports 5 v 3 v i oht ? ? ? ? 100 60 ma 5p output low current ? max total i ol for all ports 5 v 3 v i olt ? ? ? ? 100 60 ma 6 p input high voltage; all digital inputs v ih 0.65 v dd ?? v p input low voltage; all digital inputs v il ??0.35 v dd 7 p input hysteresis; all digital inputs v hys 0.06 v dd ??mv 8 9 p input leakage current; input only pins 3 |i in |? 0.1 1 a 10 p high impedance (off-state) leakage current 3 |i oz |? 0.1 1 a 11 p internal pullup resistors 4 r pu 20 45 65 k 12 p internal pulldown resistors 5 r pd 20 45 65 k 13 c internal pullup resistor to usbdp (to v usb33 ) idle tr a n s m i t r pupd 900 1425 ? ? 1575 3090 k 14 c input capacitance; all non-supply pins c in ?? 8pf 15 c ram retention voltage v ram 0.6 1.0 ? v 16 p por rearm voltage v por 0.9 1.4 2.0 v 17 d por rearm time t por 10 ? ? s table 6. dc characteristics (continued) num c parameter symbol min typical 1 max unit
MC9S08JS16 series mcu data sheet, rev. 4 electrical characteristics freescale semiconductor 10 18 p low-voltage detection threshold ? high range v dd falling v dd rising v lv d 1 3.9 4.0 4.0 4.1 4.1 4.2 v p low-voltage detection threshold ? low range v dd falling v dd rising v lv d 0 2.48 2.54 2.56 2.62 2.64 2.70 v 19 c low-voltage warning threshold ? high range 1 v dd falling v dd rising v lv w 3 4.5 4.6 4.6 4.7 4.7 4.8 v 20 p low-voltage warning threshold ? high range 0 v dd falling v dd rising v lv w 2 4.2 4.3 4.3 4.4 4.4 4.5 v 21 p low-voltage warning threshold low range 1 v dd falling v dd rising v lv w 1 2.84 2.90 2.92 2.98 3.00 3.06 v 22 c low-voltage warning threshold ? low range 0 v dd falling v dd rising v lv w 0 2.66 2.72 2.74 2.80 2.82 2.88 v 23 24 t low-voltage inhibit reset/recover hysteresis 5 v 3 v v hys ? ? 100 60 ? ? mv 1 typical values are based on characterization data at 25 c unless otherwise stated. 2 operating voltage with usb enabled can be found in section 3.11, ?usb electricals .? 3 measured with v in = v dd or v ss . 4 measured with v in = v ss . 5 measured with v in = v dd . table 6. dc characteristics (continued) num c parameter symbol min typical 1 max unit
electrical characteristics MC9S08JS16 series mcu data sheet, rev. 4 freescale semiconductor 11 figure 4. typical i oh (low drive) vs v dd ?v oh at v dd = 3 v figure 5. typical i oh (high drive) vs v dd ?v oh at v dd = 3 v i oh vs v dd -v oh (low drive) at v dd = 3 v 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 -2.2 -2.4 -2.6 -2.8 -3 i oh (ma) v dd -v oh (v) -40c 25c 85c i oh vs v dd -v oh (high drive) at v dd = 3 v 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0 -1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 i oh (ma) v dd -v oh (v) -40c 25c 85c
MC9S08JS16 series mcu data sheet, rev. 4 electrical characteristics freescale semiconductor 12 figure 6. typical i oh (low drive) vs v dd ?v oh at v dd = 5 v figure 7. typical i oh (high drive) vs v dd ?v oh at v dd = 5 v i oh vs v dd -v oh (low drive) at v dd = 5 v 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 -2.2 -2.4 -2.6 -2.8 -3 i oh (ma) v ol (v) -40c 25c 85c i oh vs v dd -v oh (high drive) at v dd = 5 v 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 -1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 i oh (ma) v dd -v oh (v) -40c 25c 85c
electrical characteristics MC9S08JS16 series mcu data sheet, rev. 4 freescale semiconductor 13 figure 8. i ol vs v ol (low drive) at v dd = 5 v figure 9. i ol vs v ol (high drive) at v dd = 5 v i ol vs v ol (low drive) at v dd = 5 v 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 -2.2 - 2. 4 -2.6 -2.8 -3 i ol (ma) v ol (v) -40c 25c 85c i ol vs v ol (high drive) at v dd = 5 v 0.00 0.05 0.10 0.15 0.20 0.25 0 -1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 i ol (ma) v ol (v) -40c 25c 85c
MC9S08JS16 series mcu data sheet, rev. 4 electrical characteristics freescale semiconductor 14 figure 10. i ol vs v ol (low drive) at v dd = 3 v figure 11. i ol vs v ol (high drive) at v dd = 3 v i ol vs v ol (low drive) at v dd = 3 v 0.0 0.2 0.4 0.6 0.8 1.0 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 -2.2 -2.4 -2.6 -2.8 -3 i ol (ma) v ol (v) -40c 25c 85c i ol vs v ol (high drive) at v dd = 3 v 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 -1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 i ol (ma) v ol (v) -40c 25c 85c
electrical characteristics MC9S08JS16 series mcu data sheet, rev. 4 freescale semiconductor 15 3.6 supply current characteristics table 7. supply current characteristics num c parameter symbol v dd (v) typical 1 1 typicals are measured at 25 c. see figure 12 through figure 10 for typical curves across voltage/temperature. max 2 2 values given here are preliminary estimates prior to completing characterization. unit 1c run supply current 3 measured at (cpu clock = 2 mhz, f bus = 1 mhz, blpe mode) ri dd 51.03 ? ma 30.83 ? 2p run supply current 3 measured at (cpu clock = 48 mhz, f bus = 24 mhz, pee mode, all module on) ri dd 5 19.93 ? ma 3 18.74 ? 3p stop2 mode supply current s2i dd 51.36 ? a 31.18 ? a 4 p stop3 mode supply current, all module off s3i dd 51.50 ? a 31.31 ? a 5 p rtc adder to stop2 or stop3 3 , 25 c 3 most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode. wait mode typical is 560 a at 5 v and 422 a at 3 v with f bus = 1 mhz. i srtc 5300 ?na 3300 ?na 6 p lvd adder to stop3 (lvde = lvdse = 1) i slvd 5 106.7 ? a 395.6 ? a 7p adder to stop3 for oscillator enabled 4 (erclken =1 and erefsten = 1) 4 values given under the following conditions: low range operation (range = 0), low power mode (hgo = 0). i sosc 55.6 ? a 35.3 ? a 8 t usb module enable current 5 5 here usb module is enabled and clocked at 48 mhz (usben = 1, usbvren =1, usbphyen = 1 and usbpu = 1), and d+ and d? pulled down by two 15.1 k resisters independently. the current consumption may be much higher when the packets are being transmitted through the attached cable. i usbe 51.5 ?ma 9 t usb suspend current 6 6 mcu enters stop3 mode, usb bus in idle state. the usb suspend current will be dominated by the d+ pullup resister. i susp 5 273.3 ? a
MC9S08JS16 series mcu data sheet, rev. 4 electrical characteristics freescale semiconductor 16 figure 12. typical run i dd for pee, fbe and blpe modes (i dd vs. v dd ) typical run i dd for pee,fbe & blpe i dd vs. v dd 0.000 5.000 10.000 15.000 20.000 25.000 2.5 3 3.5 4 4.5 5 5.5 v dd (v) i dd (ma) pee,48mhz core fbe,8mhz core blpe,2mhz core
electrical characteristics MC9S08JS16 series mcu data sheet, rev. 4 freescale semiconductor 17 3.7 external oscillator (xosc) characteristics table 8. oscillator electrical specifications (temperature range = ?40 to 85 c ambient) num c rating symbol min typ 1 1 typical data was characterized at 3.0 v, 25 c or is recommended value. max unit 1c oscillator crystal or resonator (erefs = 1, erclken = 1) low range (range = 0) high range (range = 1) fee or fbe mode 2 high range (range = 1) pee or pbe mode 3 high range (range = 1, hgo = 1) blpe mode high range (range = 1, hgo = 0) blpe mode 2 when mcg is configured for fee or fbe mode, input clock source must be divided using rdiv to within the range of 31.25 khz to 39.0625 khz. 3 when mcg is configured for pee or pbe mode, input clock source must be divided using rdiv to within the range of 1 mhz to 2 mhz. f lo f hi-fll f hi-pll f hi-hgo f hi-lp 32 1 1 1 1 ? ? ? ? ? 38.4 5 16 16 8 khz mhz mhz mhz mhz 2 ? load capacitors c 1, c 2 see crystal or resonator manufacturer?s recommendation. 3? feedback resistor low range (32 khz to 38.4 khz) high range (1 mhz to 16 mhz) r f ? ? 10 1 ? ? m 4? series resistor low range, low gain (range = 0, hgo = 0) low range, high gain (range = 0, hgo = 1) high range, low gain (range = 1, hgo = 0) high range, high gain (range = 1, hgo = 1) 8 mhz 4 mhz 1 mhz r s ? ? ? ? ? ? 0 100 0 0 0 0 ? ? ? 0 10 20 k 5t crystal start-up time 4 low range, low gain (range = 0, hgo = 0) low range, high gain (range = 0, hgo = 1) high range, low gain (range = 1, hgo = 0) 5 high range, high gain (range = 1, hgo = 1) 5 4 this parameter is characterized and not te sted on each device. proper pc board layout procedures must be followed to achieve specifications. 5 4 mhz crystal. t cstl-lp t cstl-hgo t csth-lp t csth-hgo ? ? ? ? 200 400 5 15 ? ? ? ? ms 6t square wave input clock frequency (erefs = 0, erclken = 1) fee or fbe mode 2 pee or pbe mode 3 blpe mode f extal 0.03125 1 0 ? ? ? 5 16 40 mhz mcu extal xtal crystal or resonator r s c 2 r f c 1
MC9S08JS16 series mcu data sheet, rev. 4 electrical characteristics freescale semiconductor 18 3.8 mcg specifications table 9. mcg frequency specifications (temperature range = ?40 to 85 c ambient) num c rating symbol min typical max unit 1 c average internal reference frequency ? untrimmed f int_ut 25 32.7 41.66 khz 2 p average internal reference frequency ? trimmed f int_t 31.25 ? 39.0625 khz 3 t internal reference startup time t irefst ?60100 s 4 c dco output frequency range ? untrimmed f dco_ut 25.6 33.48 42.66 mhz 5 p dco output frequency range ? trimmed f dco_t 32 ? 40 mhz 6c resolution of trimmed dco output frequency at fixed voltage and temperature (using ftrim) f dco_res_t ? 0.1 0.2 %f dco 7c resolution of trimmed dco output frequency at fixed voltage and temperature (not using ftrim) f dco_res_t ? 0.2 0.4 %f dco 8p total deviation of trimmed dco output frequency over voltage and temperature f dco_t ? 0.5 ?1.0 2 %f dco 9c total deviation of trimmed dco output frequency over fixed voltage and temperature range of 0?70 c f dco_t ? 0.5 1 %f dco 10 c fll acquisition time 1 1 this specification applies any time the fll reference source or reference divider is changed, trim value changed or changing from fll disabled (blpe, blpi) to fll enabl ed (fei, fee, fbe, fbi). if a crystal/reson ator is being used as the reference, this specification assumes it is already running. t fll_acquire ?? 1ms 11 d pll acquisition time 2 2 this specification applies to any time the pll vco divider or reference divider is changed, or changing from pll disabled (blpe, blpi) to pll enabled (pbe, pee). if a crystal/resonator is being used as the reference, this specificat ion assumes it is already running. t pll_acquire ?? 1ms 12 c long term jitter of dco output clock (averaged over 2ms interval) 3 c jitter ?0.020.2 %f dco 13 d vco operating frequency f vco 7.0 ? 55.0 mhz 14 d pll reference frequency range f pll_ref 1.0 ? 2.0 mhz 15 t long term accuracy of pll output clock (averaged over 2 ms) f pll_jitter_2ms ? 0.590 4 ?% 16 t jitter of pll output cl ock measured over 625 ns 5 f pll_jitter_625ns ? 0.566 4 ?% 17 d lock entry frequency tolerance 6 d lock 1.49 ? 2.98 % 18 d lock exit frequency tolerance 7 d unl 4.47 ? 5.97 % 19 d lock time ? fll t fll_lock ?? t fll_acquire+ 1075(1/ f int_t) s 20 d lock time ? pll t pll_lock ?? t pll_acquire+ 1075(1/ f pll_ref) s 21 d loss of external clock minimum frequency ? range = 0 f loc_low (3/5) x f int ? ? khz 22 d loss of external clock minimum frequency ? range = 1 f loc_high (16/5) x f int ? ? khz
electrical characteristics MC9S08JS16 series mcu data sheet, rev. 4 freescale semiconductor 19 3.9 ac characteristics this section describes ac timing char acteristics for each peripheral system. 3.9.1 control timing 3 jitter is the average deviation from t he programmed frequency measured over the specified interval at maximum f bus . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the fll circuitry via v dd and v ss and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. 4 jitter measurements are bas ed upon a 48 mhz clock frequency. 5 625 ns represents 5 time quanta for can applications, under wo rst case conditions of 8 mhz can bus clock, 1 mbps can bus speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a synchronization edge and the sample point of a bit using 8 time quanta per bit. 6 below d lock minimum, the mcg is guaranteed to enter lock. above d lock maximum, the mcg will not enter lock. but if the mcg is already in lock, then the mcg may stay in lock. 7 below d unl minimum, the mcg will not exit lock if already in lock. above d unl maximum, the mcg is guaranteed to exit lock. figure 13. control timing num c parameter symbol min typical 1 1 typical values are based on characterization data at v dd = 5.0 v, 25 c unless otherwise stated. max unit 1 d bus frequency (t cyc = 1/f bus )f bus dc ? 24 mhz 2 d internal low-power oscillator period t lpo 700 ? 1300 s 3d external reset pulse width 2 (t cyc = 1/f self_reset ) 2 this is the shortest pulse that is guarant eed to be recognized as a reset pin request. shorter pulses are not guaranteed to override reset requests from internal sources. t extrst 1.5 t self_reset ??ns 4 d reset low drive t rstdrv 66 t cyc ??ns 5d active background debug mode latch setup time t mssu 25 ? ? ns 6d active background debug mode latch hold time t msh 25 ? ? ns 7d irq pulse width asynchronous path 2 synchronous path 3 3 this is the minimum pulse width guaranteed to pass through t he pin synchronization circuitry. shorter pulses may or may not be recognized. in stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. t ilih, t ihil 100 1.5 t cyc ??ns 8d kbipx pulse width asynchronous path 2 synchronous path 3 t ilih, t ihil 100 1.5 t cyc ??ns 9c port rise and fall time (load = 50 pf) 4 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) 4 timing is shown with respect to 20% v dd and 80% v dd levels. temperature range ?40 c to 85 c. t rise , t fall ? ? 3 30 ? ? ns
MC9S08JS16 series mcu data sheet, rev. 4 electrical characteristics freescale semiconductor 20 figure 14. reset timing figure 15. irq/kbipx timing 3.9.2 timer/pwm (tpm) module timing synchronizer circuits determine the s hortest input pulses that can be re cognized or the fastest clock that can be used as the optional external source to the timer counter. these synchr onizers operate from the current bus rate clock. figure 16. timer external clock table 10. tpm input timing num c function symbol min max unit 1 d external clock frequency f tpmext dc f bus /4 mhz 2 d external clock period t tpmext 4?t cyc 3 d external clock high time t clkh 1.5 ? t cyc 4 d external clock low time t clkl 1.5 ? t cyc 5 d input capture pulse width t icpw 1.5 ? t cyc t extrst reset pin t ihil irq/kbipx t ilih irq/kbipx t tpmext t clkh t clkl tpmxclk
electrical characteristics MC9S08JS16 series mcu data sheet, rev. 4 freescale semiconductor 21 figure 17. timer input capture pulse 3.10 spi characteristics table 11 and figure 18 through figure 21 describe the timing require ments for the spi system. t icpw tpmxchn t icpw tpmxchn
MC9S08JS16 series mcu data sheet, rev. 4 electrical characteristics freescale semiconductor 22 table 11. spi electrical characteristic num 1 1 refer to figure 18 through figure 21 . c characteristic 2 2 all timing is shown with respect to 20% v dd and 80% v dd , unless noted; 50 pf load on all spi pins. all timing assumes slew rate control disabled and high drive strength enabled for spi output pins. symbol min typical max unit 1d operating frequency 3 master slave 3 the maximum frequency is 8 mhz when input filter on spi pins is disabled. f op f op f bus /2048dc ? ? f bus /2 f bus /4 hz 2d cycle time master slave t sck t sck 2 4 ? ? 2048 ? t cyc 3d enable lead time master slave t lead t lead ? ? 1/2 1/2 ? ? t sck 4d enable lag time master slave t lag t lag ? ? 1/2 1/2 ? ? t sck 5d clock (spsck) high time master slave t sckh ? 1/2 t sck ? 25 1/2 t sck 1/2 t sck ? ? ns 6d clock (spsck) low time master slave t sckl ? 1/2 t sck ? 25 1/2 t sck 1/2 t sck ? ? ns 7d data setup time (inputs) master slave t si(m) t si(s) 30 30 ? ? ? ? ns 8d data hold time (inputs) master slave t hi(m) t hi(s) 30 30 ? ? ? ? ns 9 d access time, slave 4 4 time to data active from high-impedance state. t a ??40ns 10 d disable time, slave 5 5 hold time to high-impedance state. t dis ??40ns 11 d data setup time (outputs) master slave t so t so ? ? ? ? 25 25 ns 12 d data hold time (outputs) master slave t ho t ho ?10 ?10 ? ? ? ? ns
electrical characteristics MC9S08JS16 series mcu data sheet, rev. 4 freescale semiconductor 23 figure 18. spi master timing (cpha = 0) figure 19. spi master timing (cpha = 1) sck (output) sck (output) miso (input) mosi (output) ss 1 (output) msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) notes: 2. lsbf = 0. for lsbf = 1, bit or der is lsb, bit 1, ..., bit 6, msb. 1. ss output mode (modfen = 1, ssoe = 1). 1 2 3 5 6 7 10 12 5 10 4 4 sck (output) sck (output) miso (input) mosi (output) msb in (2) bit 6 . . . 1 lsb in msb out (2) lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) ss (1) (output) 1. ss output mode (modfen = 1, ssoe = 1). 2. lsbf = 0. for lsbf = 1, bit or der is lsb, bit 1, ..., bit 6, msb. notes: 2 1 3 4 5 6 7 10 12 5 4
MC9S08JS16 series mcu data sheet, rev. 4 electrical characteristics freescale semiconductor 24 figure 20. spi slave timing (cpha = 0) figure 21. spi slave timing (cpha = 1) 3.11 flash specifications this section provides details about program/erase times and program-erase endurance for the flash memory. program and erase operations do not require any special power sources other than the normal v dd supply. sck (input) sck (input) mosi (input) miso (output) ss (input) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) note: slave see note 1. not defined but normally msb of character just received 1 2 3 4 6 7 8 9 10 12 5 5 4 sck (input) sck (input) mosi (input) miso (output) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 see (cpol = 0) (cpol = 1) ss (input) note: slave note 1. not defined but normally lsb of character just received 1 2 3 4 6 7 8 9 10 12 4 5 5
electrical characteristics MC9S08JS16 series mcu data sheet, rev. 4 freescale semiconductor 25 3.12 usb electricals the usb electricals for the s08usbv1 module conf orm to the standards documented by the universal serial bus implementers forum. for the most up-to-date standards, visit http://www.usb.org. if the freescale s08usbv1 implementation requires add itional or deviant electrical characteristics, this space would be used to communicate that information. table 12. flash characteristics num c characteristic symbol min typical 1 1 typical values are based on characterization data at v dd = 5.0 v, 25 c unless otherwise stated. max unit 1 d supply voltage for program/erase v prog/erase 2.7 ? 5.5 v 2 d supply voltage for read operation v read 2.7 ? 5.5 v 3 d internal fclk frequency 2 2 the frequency of this clock is controlled by a software setting. f fclk 150 ? 200 khz 4 d internal fclk period (1/fclk) t fcyc 5 ? 6.67 s 5 p byte program time (random location) 2 t prog 9 t fcyc 6 p byte program time (burst mode) 2 t burst 4 t fcyc 7 p page erase time 3 3 these values are hardware state machin e controlled. user code does not n eed to count cycles. this information supplied for calculating approximate time to program and erase. t page 4000 t fcyc 8 p mass erase time 2 t mass 20,000 t fcyc 9 c program/erase endurance 4 t l to t h = ?40 c to 85 c t = 25 c 4 typical endurance for flash was evaluated for this produc t family on the 9s12dx64. for additional information on how freescale semiconductor defines typical endurance, please refer to engineering bulletin eb619/d, ty p i c a l endurance for nonvolatile memory . ? 10,000 ? ? 100,000 ? ? cycles 10 c data retention 5 5 typical data retention values are based on intrinsic capab ility of the technology measur ed at high temperature and de-rated to 25 c using the arrhenius equation. for additional information on how freescale semiconductor defines typical data retention, please refer to engineering bulletin eb618/d, typical data retention for nonvolatile memory. t d_ret 15 100 ? years table 13. internal usb 3.3 v voltage regulator characteristics symbol min typical max unit regulator operating voltage v regin 3.9 ? 5.5 v v reg output v regout 33.33.6 v v reg filter capacitor c usbreg ? 100 ? pf v usb33 input with internal v reg disabled v usb33in 33.33.6 v
MC9S08JS16 series mcu data sheet, rev. 4 ordering information freescale semiconductor 26 4 ordering information this section contains ordering information for devi ce numbering system. see below for an example of the device numbering system. 4.1 package information 4.2 mechanical drawings this following pages contain me chanical specifications for mc9s 08js16 series package options. ? 24-pin qfn (quad flat no-lead) ? 20-pin w-soic (wide body small outline integrated circuit) table 14. external 3.3 v voltage regulator supply for v usb33 pin symbol min typical max unit external 3.3 v regulator output current ? 39 ? ? ma table 15. package descriptions pin count package type abbreviation designator case no. document no. 24 quad flat no-leads qfn fk 1982-01 98arl10608d 20 wide body small outline integrated circuit w-soic wj 751d 98asb42343b mc temperature range family memory status core (c = ?40 c to 85 c) (9 = flash-based) 9 s08 js xx (mc = fully qualified) package designator (see ta bl e 1 5 ) 16 approximate memory size (in kb) c (l) usb bootloader supported at 3.3 v

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